Central processing units (CPUs) generally utilize translation lookaside buffers (TLBs) to cache page table translations from virtual addresses (VAs) to physical addresses (PAs) using page tables. In virtualized systems, nested page tables may be used to support a second level of translation associated with a guest physical address space. For example, the nested page tables may be used to map VAs to guest or intermediate PAs (IPAs) and to map the IPAs to the PAs. Generally, the mapping from the VAs to the IPAs is controlled by a guest operating system (OS) executing within a virtual machine (VM) and the mapping from the IPAs to the PAs is controlled by a hypervisor. Even though the PAs are derived from the IPAs, for a given VA, an entry storing a mapping between the VA and a PA corresponding to an underlying IPA cannot be easily found in the TLB.